In the last years the memory market has been characterized by an increasing interest in high density devices and technology scaling has become more and more aggressive, both for memory core and circuitry, especially for the memory devices of the NAND type. While the technology is continuously improving to reduce the memory size, new solutions are studied to reduce the area of the related analog circuitry, which is not exclusively dependent on technology, but mainly on the specifically adopted layouts and architectures.
At the same time, while devices are continuously shrinking, the performance requirements are getting more and more challenging.
One of the important features for NAND memories is the program throughput, which has been improved in the last years by increasing the page size, which is the amount of data that can be written or read in a parallel mode from a memory array.
Another relevant contribution is given by the multiple plane architecture and the related parallel plane page programming, which allows programming more pages at a time, each page belonging to a different matrix array.
However, in a memory device with multiple planes not only the row decoder circuitry but also all the voltage switches for the selected and unselected word lines are replicated for each plane and enabled only in the selected plane or planes, with an increasing of the complexity of the memory architecture as a whole.
The known configurations of memory devices with multiple planes thus require a high area and complicate the word line selection circuitry placement in the memory device floorplane.